Satish Chandra Tiwari

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In this paper, a single edge-triggered, static D flip-flop design suitable, for low power and low area requirements is proposed. Advantageously, the flip-flop is realized using only ten transistors. The flip-flop is implemented using Master-Slave configuration and can be used for lower cost memory and microprocessor chips. The 0.6-micron technology is used(More)
ETHNOPHARMACOLOGICAL RELEVANCE Elephantopus mollis, Spilanthes africana, Urena lobata, Momordica multiflora, Asystasia gangetica and Brillantaisia ovariensis are used in Cameroonian traditional medicine for the treatment of bone diseases and fracture repair. The aim of this study was to evaluate the effect of ethanolic extracts of six Cameroonian medicinal(More)
The paper introduces a new low power, high density double edge triggered, (DET) flip-flop. The proposed DET flip-flop is implemented using lesser number of transistors as compared to other state of the art double edge triggered flip-flops designs. Simulation at 250MHz frequency using 180nm/1.8V CMOS technology with BSIM 3v3 parameters, the proposed design(More)
The paper presents a new design for implementing a static Master-Slave Flip-flop with reduced transistor count for low power and high performance applications. The proposed flip-flop is realized using only eleven transistors (including an inverter to produce complementary clock signals locally) hence reducing the manufacturing cost. SPICE simulation results(More)
The paper proposes a new methodology for optimization and characterization of flip-flops that can be utilized in designing EDA tool for NOC. In automated RTL to GDS II design space there is requirement of libraries with large number of cells. Now each design can have large number of different driving strength cells. Hence the paper proposes a methodology by(More)
Digital and analog designers are always interested in automated optimization of transistor width values for customized requirements. SPICE tools are now embedded with certain options [like L-M algorithm and parametric analysis] by virtue of which automated width optimization can be performed upto a certain extent. Whereas when the optimization requirements(More)
The paper presents a new automated transistor width optimization methodology for SoC. The methodology is based on Logical Effort theory. The proposed methodology is completely automation based and uses different procedural blocks written in TCL (tool command language). The methodology requires SPICE netlist as input and optimizes transistor widths for(More)
Choice of a combinational circuit among large number of circuits having same functionality has been always a complex and time consuming task for digital designers. Different circuits (where they are initially proposed) were optimized using different techniques and objectives. Moreover there merits vary as per optimization methodology and technique(More)
The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C(2)MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C(2)MOS based flip-flop designs mC(2)MOSff1(More)
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