Sasikiran Burugapalli

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This paper focuses on implementing an unsigned 24+8×8 quad-rail (i.e., accumulator consists of 12 quad-rail signals, while the multiplier and multiplicand are each 4 quadrail signals) Multiply and Accumulate (MAC) unit using the asynchronous NULL Convention Logic (NCL) paradigm. The design utilizes the array-structured algorithm for partial product(More)
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