Sasha Novakovsky

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In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV-Extract and is part of a comprehensive Formal Equivalence Verification (FEV) system developed at Intel to verify modern microprocessor designs. FEV-Extract employs a powerful(More)
In general, we lack in EDA industry tools and automated solutions in μArchitectural domain. In this paper, we elaborate on our attempt to advance performance simulation based statistical analysis techniques. On one hand, we utilize the content knowledge of μArchitectural specification (e.g., explicit specification of the major transactions), and on(More)
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