Sara Pashmineh

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This paper presents a high-voltage (HV) driver for switching a buck converter. The circuit is based on 3-stacked CMOS using gate control circuits to drive maximum current which indicates minimized on-resistance of the HV-driver thus achieving faster switching. The circuit is designed and fabricated using 65 nm CMOS TSMC process technology with a nominal(More)
This paper presents the design of a high-voltage (HV) rail-to-rail error amplifier. This circuit controls the output signal of a low drop-out voltage regulator (LDO) according to the reference voltages and based on stacked standard transistors. The circuit is designed using 65 nm CMOS process technology with a nominal voltage of 2.5 V and is optimized for(More)
This paper presents the design of two high-voltage level shifters suitable for a wide range of supply voltages. In view of certain drawbacks identified during the design, implementation, simulation and measurement of a 3-stacked CMOS driver using capacitive feedback level shifters, improved high-voltage level shifters are designed. These circuits are(More)
This paper presents the design of a high-voltage differential amplifier using six different pre-input stage circuits to reduce high-voltage input levels to low-voltage signals. The proposed circuits are designed using 65 nm CMOS process technology with a nominal voltage of 2.5 V and a supply voltage of 5 V. The designs are based on stacked low-voltage(More)
This paper presents a low drop-out voltage regulator (LDO) suitable for input voltages twice the nominal operating voltage of the CMOS technology. High GBW and good DC accuracy in line and load regulation is achieved by using 3-stage error amplifiers. Two feedback loops are used to improve stability. High voltage compatibility is established by stacking two(More)
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