Sao-Jie Chen

Learn More
A bidirectional channel network-on-chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication. In a BiNoC, each communication channel allows to be dynamically self-reconfigured to transmit flits in either direction. This added flexibility promises better bandwidth utilization, lower packet delivery latency, and higher packet(More)
A Bidirectional channel Network-on-Chip (BiNoC) architecture is proposed to enhance the performance of on-chip communication. The BiNoC allows each communication channel to be dynamically selfconfigured to transmit flits in either direction in order to better utilize on-chip hardware resources. This added flexibility promises better bandwidth utilization,(More)
In this paper, the gate matrix layout is formulated as a planning problem where a "plan" (the solution steps) is generated to achieve a "goal" (the gate matrix layout) that consists of subgoals interacting each other. Each subgoal corresponds to the placement of a gate to a slot. or to the routing of a net connecting gates. The interaction among subgoals is(More)
The timing-convergence problem arises because estimations made during logic synthesis may not be met during physical design. In this paper, an efficient rewiring engine is proposed to explore maximal freedom after placement. The most important feature of this approach is that the existing placement solution is left intact throughout the optimization. A(More)
In this paper, we propose a novel framework for fast multilevel routing considering crosstalk and performance optimization. To handle the crosstalk minimization problem, we incorporate an intermediate stage of layer/track assignment into the multilevel routing framework. For performance-driven routing, we propose a novel minimum-radius minimum-cost spanning(More)
The design of multiprocessor architectures differs from uniprocessor systems in that the number of processors and their interconnection must be considered. This leads to an enormous increase in the design-space exploration time, which is exponential in the total number of system components. The methodology proposed here, called <italic>Intelligent(More)
In this paper, we present a VLSI architecture for the separable two-dimensional Discrete Wavelet Transform (DWT) decomposition. Using a computation-schedule table, we showed how the proposed separable architecture uses only a minimal number of filters to generate all levels of DWT computations in real time. For the computation of an N x N 2-D DWT with a(More)