Santanu Sarkar

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This paper presents design of an 8-bit 1.8 V segmented current steering (CS) digital-to-analog converter (DAC)using 0.18 μm double poly five metal CMOS technology. The DAC has been segmented as 6+2 to achieve optimum performance for minimum area. The simulation result shows a maximum DNLof 0.30 LSB and an INL of 0.33 LSB. The midcode glitch is0.27 pV(More)
This paper presents an 8 bit 1.8 V 500 MSPS digitalto analog converter using 0.18μm double poly five metal CMOS technology for frequency domain applications. The proposed DAC is composed of four unit cell matrix. A novel decoding logic is used to remove the Inter Block Code Transition (IBT) glitch. The proposed DAC shows less number of switching for a(More)
This paper describes the design techniques of a segmented current steering (CS) digital-to-analog converter (DAC)with optimum sizing of the current sources. The DAC has been designed in 0.18 μm CMOS n-well technology provided by National Semiconductor. The 10-bit DAC is segmented as 5+5, where the 5-LSB bits are implemented in binary and the 5-MSB(More)
Business Process Outsourcing (BPO) sector is thriving in India but before the IteS market can really open out beyond the call centre model of business, sparks of trade unionism are now visible in the BPO and call centre industry in India. Nevertheless, there is a widely held view that important changes are occurring in the character of employee attitudes(More)
The effect of bias node voltage fluctuations on the performance of the current steering (CS) DAC is studied in this work. For that purpose a 10-bit segmented CS-DAC has been designed in 0.18 μm CMOS n-well technology provided by National Semiconductor. All current sources connected to the same bias cell act as correlated noise sources and generates(More)
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