Sanof Mohamed

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A CDEC gate, or a condition decoder, being a product of an AND and NAND of literals, has been introduced in the logic array of the high-speed EPLD CY7C361 chip from Cypress. We give an algorithm for the minimization of SUM-OF-CDEC (SOC) expressions. This algorithm produced the minimum solutions on all small single-output functions, as required by this chip.(More)
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