Sanku Mukherjee

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Resetting flip flops in high speed clock domain across wide silicon area is a challenge due to significant delay variations between the clock and reset signals. In this paper, a novel method of transmitting Reset Through the Clock (RTC) tree is proposed. At the root of the clock tree, multiplexing circuit encodes reset as pulses of width smaller than clock(More)
A bi-modal x32 memory interface supports 6.4-Gbps GDDR5 signaling as well as 2.4-Gbps DDR3 signaling with a 1.5V IO supply. The interface incorporates a novel driver and pre-driver structure that supports one-tap equalization and presents very small capacitive loading to the pins. The entire interface, including both data and request channels achieves(More)
Single-ended memory interfaces have gone through a remarkable increase in data rates over the last decade increasing the challenges faced by system designers and OEMs. One of the major challenges in single-ended system design is optimizing the reference voltage level (Vref) in the receiver. The traditional method to choose Vref is to sweep the reference(More)
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