Sankaralingam Panneerselvam

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Storage-class memory technologies such as phase-change memory and memristors present a radically different interface to storage than existing block devices. As a result, they provide a unique opportunity to re-examine storage architectures. We find that the existing kernel-based stack of components, well suited for disks, unnecessarily limits the design and(More)
The rise of multi-core processors has shifted performance efforts towards parallel programs. However, single-threaded code, whether from legacy programs or ones difficult to parallelize, remains important. Proposed asymmetric multicore processors statically dedicate hardware to improve sequential performance, but at the cost of reduced parallel performance.(More)
Dynamic resource scaling enables provisioning extra resources during peak loads and saving energy by reclaiming those resources during off-peak times. Scaling the number of CPU cores is particularly valuable as it allows power savings during low-usage periods. Current systems perform scaling with a slow hotplug mechanism, which was primarily designed to(More)
The inexorable demand for computing power has lead to increasing interest in accelerator-based designs. An accelerator is specialized hardware unit that can perform a set of tasks with much higher performance or power efficiency than a general-purpose CPU. They may be embedded in the pipeline as a functional unit, as in SIMD instructions, or attached to the(More)
With low-latency storage-class memory, software can be a major contributor to access latency. To minimize latency, a file system architecture has to provide flexibility in customizing the file system interface and semantics to application needs so as to cut down generic overheads. We have taken initial steps towards realizing such a design and present(More)
The rise of multicore processors has lead to techniques that dynamically vary the set and characteristics of cores or threads available to the operating system. For example, Core Fusion merges multiple cores for faster processing. While the mechanics of the change, such as merging two cores into a more powerful core, can be handled by a virtualization(More)
A Multidisciplinary Design Optimization (MDO) process has been conceived for configuration design of an Air-Breathing Hypersonic Technology Demonstrator Vehicle. The design problem has been cast in Multi-Discipline Feasible formulation and analysis models based on engineering methods have been developed. Zeroth order correction factors, derived form CFD(More)
The phenomenon of Dark Silicon has made processors over-provisioned with compute units that cannot be used at full performance without exceeding power limits. Such limits primarily exist to exercise control over heat dissipation. Current systems support mechanisms to ensure system-wide guarantees of staying within the power and thermal limit. However, these(More)
Current processors provide a variety of different processing units to improve performance and power efficiency. For example, ARM's big.LITTLE, AMD's APUs, and Oracle's M7 provide heterogeneous processors, on-die GPUs, and on-die accelerators. However, the performance experienced by programs using these processing units can vary widely due to contention from(More)
Processor designs are moving away from homogeneity and are embracing heterogeneity. Such designs can take various forms like asymmetric CPU clusters targeting different power-performance trade-offs (e.g. big.LITTLE), programmable accelerators (e.g. GPU, DSP), fixed function accelerators (e.g. crypto) and custom logic (e.g. FPGA). Heterogeneous processors(More)