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As technology scales below 100nm and operating frequencies Increase, correct operation of nano-CMOS will be compromised due reduced device-to-device distance, imperfections, and low noise and voltage margins. Unlike traditional faults and defects, these errors are expected to be transient in nature. Unlike radiation related upset errors, the propensity of… (More)

- Sanjukta Bhanja, N. Ranganathan
- IEEE Trans. VLSI Syst.
- 2003

Switching activity estimation is an important aspect of power estimation at circuit level. Switching activity in a node is temporally correlated with its previous value and is spatially correlated with other nodes in the circuit. It is important to capture the effects of such correlations while estimating the switching activity of a circuit. In this paper,… (More)

We propose a novel formalism, based on probabilistic Bayesian networks, to capture, analyze, and model dynamic errors at nano logic for probabilistic reliability analysis. It will be important for circuit designers to be able to compare and rank designs based on the expected output error, which is a measure of reliability. We propose an error model to… (More)

- Saket Srivastava, Arjun Asthana, Sanjukta Bhanja, Sudeep Sarkar
- ISCAS
- 2011

- Thara Rejimon, Karthikeyan Lingasubramanian, Sanjukta Bhanja
- IEEE Trans. VLSI Syst.
- 2009

- Thara Rejimon, Sanjukta Bhanja
- 18th International Conference on VLSI Design held…
- 2005

We propose a novel single event fault/error model based on logic induced fault encoded directed acyclic graph (LIFE-DAG) structured probabilistic Bayesian networks, capturing all spatial dependencies induced by the circuit logic. The detection probabilities also act as a measure of soft error susceptibility (an increased threat in nanodomain logic block)… (More)

- Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan
- 18th International Conference on VLSI Design held…
- 2005

We propose a novel, non-simulative, probabilistic model for switching activity in sequential circuits, capturing both spatio-temporal correlations at internal nodes and higher order temporal correlations due to feedback. This model, which we refer to as the temporal dependency model (TDM), can be constructed from the logic structure and is shown to be a… (More)

- Sanjukta Bhanja, Marco Ottavi, Fabrizio Lombardi, Salvatore Pontarelli
- Proceedings of the Design Automation & Test in…
- 2006

In this paper, different circuit arrangements of quantum-dot cellular automata (QCA) are proposed for the so-called coplanar crossing. These arrangements exploit the majority voting properties of QCA to allow a robust crossing of wires on the Cartesian plane. This is accomplished using enlarged lines and voting. Using a Bayesian network (BN) based… (More)

We propose a novel fault/error model based on a graphical probabilistic framework. We arrive at the Logic Induced Fault Encoded Directed Acyclic Graph (LIFE-DAG) that is proven to be a Bayesian network, capturing all spatial dependencies induced by the circuit logic. Bayesian Networks are the minimal and exact representation of the joint probability… (More)

- Sanjukta Bhanja, N. Ranganathan
- ICCD
- 2002

We represent switching activity in VLSI circuits using a graphical probabilistic model based on Cascaded Bayesian Networks (CBN’s). We develop an elegant method for maintaining probabilistic consistency in the interfacing boundaries across the CBN’s during the inference process using a tree-dependent (TD) probability distribution function. A tree-dependent… (More)