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During system design, one or more portions of the system may be implemented with standard components that have a fixed pin structure and communication protocol. This paper described a new technique, interface process generation, for interfacing standard components that have incompatible protocols. Given an HDL description of the two protocols, we present a(More)
When estimating a hardware implementation from be-havioral descriptions, an important decision is the selection of a clock cycle to schedule the datapath operations into control steps. Prior to scheduling, most existing be-havioral synthesis systems either require the designer to specify the clock cycle explicitly or require that the delays of the operators(More)
System-level partitioning groups processes and variables in the system specification into modules representing chips and memories. Communication between the modules is represented by abstract communication channels, which are merged and implemented as a bus to minimize interconnect. Given a set of channels, bus generation synthesizes the bus structure, by(More)
This report describes a presentation on the design methodology and the user's view of the SpecSyn system design framework. Given an abstract specication of a system, we present specication capture and the subsequent renements that will result in synthesizable descriptions. The advantages of the underlying methodology compared to current approaches are(More)
System-level design issues are gaining increasing attention, as behavioral synthesis tools and methodologies mature. We present the SpecSyn system-level design environment, which supports the new specify-explore-reene (SER) design paradigm. This three-step approach to design includes precise speciication of system functionality, rapid exploration of(More)
VHDL and other hardware description languages are commonly used as speciication languages during system design. However, the underlying model of those languages does not directly support the speciication of embedded systems, making the task of specifying such systems tedious and error-prone. We introduce a new conceptual model, called Program-State Machines(More)