Sanjeev Rai

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This paper presents a novel approach to design robust source coupled logic for implementing ultra low power circuits. In this paper, we proposed a dynamic threshold source coupled logic and analyses the performance of dynamic threshold source coupled logic with previous source coupled logic for ultra low power operation. Dynamic threshold source coupled(More)
This paper presents a new hardware architecture for a unified multiplier, which operates in two types of finite field: GF (P) and GF (2<sup>m</sup>). We present a simple but highly useful modification of the conventional hardware implementation of accumulation in finite field over GF (P) and GF (2<sup>m</sup>). This new design uses parallel one's counters(More)
1 Department of Electronics & Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, India srai@mnnit.ac.in 2 Apache Design Solutions, Noida, India govind@gmail.com 3 Department of Electronics & Communication Engineering, Motilal Nehru National Institute of Technology, Allahabad, India ramishra@mnnit.ac.in 4 Director National(More)
The characteristics of junctionless(JL) SON(Silicon on Nothing) FinFET, JL Bulk FinFET and SOI(Silicon on Insulator) JNT(Junctionless nanowire transistor) transistors were compared. A Silicon on nothing transistor have substrate with air filled dielectric. JL SON FinFET have better on/off current ratio and short channel effect (SCE) by reducing channel(More)
In this paper, a simple structure for short channel junction-less double gate (JLDG) MOSFET is proposed. Further expression for surface potential of JLDG has been derived using 2D Poisson's equation. Based on the proposed analytical model for surface potential distribution along channel thickness and channel length is derived. The proposed junction-less(More)
In this paper, we have primarily focused on the implementation of techniques to reduce power-delay product of sub-threshold source coupled logic (STSCL) circuits. Here the comparisons have been drawn to derive the performance of STSCL, STSCL-SFB (sub-threshold source coupled logic circuits with source follower buffer at output stage) and STSCL-PUSHPULL(More)
In this paper expression for surface potential of a junction less cylindrical surrounding gate (JLCSG) MOSFET has been derived using 2D Poisson's equation. The proposed JLCSG MOSFET has no source/drain junction as the doping of channel region is the same as that of source/drain region. The analytical results are compared with the numerical solution using 2D(More)
In this paper, the electrostatic performance of junctionless dual material double gate (JLDMDG) silicon on insulator (SOI) is compared with that of JLDMDG silicon on nothing (SON) MOSFET. The 2D device simulation is used for the comparison of major electrostatic figure of merits such as threshold voltage (VTh), subthreshold swing, Drain Induced Barrier(More)
Double-gate FinFET is a novel device structure used in the nanometer regime, whereas the conventional CMOS technology&apos;s performance deteriorates due to increased short channel effects (SCEs). Double-gate (DG) FinFETs has better SCEs performance compared to the conventional CMOS and stimulates technology scaling. In this paper, we are designing 32nm(More)