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Abstract In this paper, we present the implementation and silicon measurements results of a 64bit processor fabricated in 0.18μm technology . The processor employs a delay-error detection and correction scheme called Razor to eliminate voltage safety margins and scale voltage 120mV below the first failure point. It achieves 44% energy savings over the worst(More)
Traditional adaptive methods that compensate for PVT variations need safety margins and cannot respond to rapid environmental changes. In this paper, we present a design (RazorII) which implements a flip-flop with in situ detection and architectural correction of variation-induced delay errors. Error detection is based on flagging spurious transitions in(More)
Much research has been done lately concerning analysis and optimization techniques for on-chip power grid networks.However, all of these approaches assume a particular model or behavior of the power delivery.In this paper, we describe the first detailed full-die dynamic model of an industrial microprocessor design, including package and non-uniform decap(More)
A 2.6pJ/Inst subthreshold sensor processor designed for energy efficiency has been fabricated. A two-stage micro-architecture was implemented to mitigate the impact of process variation in subthreshold operation. Careful library cell selection and robust SRAM design enabled fully functional operation from 1.2V to 200mV. We analyze the variation in frequency(More)
Power supply integrity analysis is critical in modern high perfor-mance designs. In this paper, we propose a stochastic approach to obtain statistical information about the collective IR and LdI/dt drop in a power supply network. The currents drawn from the power grid by the blocks in a design are modelled as stochastic processes and their statistical(More)
Subthreshold circuits have drawn a strong interest in recent ultralow power research. In this paper, we present a highly efficient subthreshold microprocessor targeting sensor application. It is optimized across different design stages including ISA definition, microarchitecture evaluation and circuit and implementation optimization. Our investigation(More)
OBJECTIVES To investigate the seroprevalence of hepatitis B surface antigen (HBsAg) in pregnant women and possible risk factors for perinatal hepatitis B virus (HBV) transmission. METHODS Four thousand pregnant women were evaluated using history, examination, and test for serum HBsAg using commercial enzyme immunoassay kits. For HBsAg positive women,(More)
In high-performance microprocessor cores, the on-die supply voltage seen by the transistors is non-ideal and exhibits significant fluctuations. These supply fluctuations are caused by sudden changes in the current consumed by the microprocessor in response to variations in workloads. This non-ideal supply can cause performance degradation or functional(More)
Sudden variations in current (large di/dt) can lead to significant power supply voltage droops and timing errors in modern microprocessors. Several papers discuss the complexity involved with developing test programs, also known as stress marks, to stress the system. Authors of these papers produced tools and methodologies to generate stress marks(More)