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—The IBM POWER6 processor is a dual-core, 341 mm 2 , 790 million transistor chip fabricated using IBM's 65 nm partially-depleted SOI process. Capable of running at frequencies up to 5 GHz in high performance applications, it can also operate under 100 W for power-sensitive applications. Traditional power-intensive and deep-pipelining techniques used in high(More)
A Wallace tree multiplier using modified booth algorithm is proposed in this paper. It is an improved version of tree based Wallace tree multiplier [1] architecture. This paper aims at additional reduction of latency and power consumption of the Wallace tree multiplier. This is accomplished by the use of booth algorithm, 5:2, 4:2, and 3:2 compressor adders.(More)
— Solar DC pump system is easy to install and operates full automatically without watching. Solar DC pump needs less solar panels to run than the AC pump. A simulation model is necessary for the manufacturer to assess the performance of solar pump controller. Solar DC Pump consists of solar PV Modules, solar DC controller, and submersible DC pump. Solar(More)
Arithmetic operations are becoming a bigger concern in the digital system for applications like ALU (Arithmetic and Logic Unit) and DSP (Digital Signal Processing). Our work focuses on novel 4-2 and 5-2 Compressors(CM) applied in multiplication architectures such as Unsigned Wallace tree multiplier, Vedic mathematics using Urdhva Triyakbyam sutra, and(More)
The versatile solution to path planning of multi robots for industrial based services are presented in this paper. The authors are motivated to solve the challenges of multi robots path planning issues. The hardware based amenable algorithm for optimal path planning of multi robot with behavioural control is developed. The heuristic approach based leader(More)
A 32 bit high speed area efficient Wallace tree multiplier is designed using verilog HDL and implemented in FPGA. The circuit is designed using carry save adder architecture and finally with one look ahead carry adder. The design is an improved version of tree based Wallace tree multiplier architecture. This paper aims at high speed multiplication and an(More)
Based on most of the literature, this paper reviewed the progress made in following aspects: cognition to cyanobacteria recruitment, various traps for studying cyanobacteria recruitment in lakes, recruitment patterns of some species of cyanobacteria and the driving factors for recruitment. Additionally, perspective studies of cyanobacteria recruitment in(More)
Many of the today’s real time signal processing algorithm included multiplication as its processing heart. In case of signal and image processing, it mostly used functional unit. In this paper we are simulating different multiplication algorithm with their effective architecture. Also paper introducing new multiplication technique using barrel shifter which(More)