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We propose a new hybrid parallelization method for H.264/AVC decoder for UHD (3840×2160) resolution on the proposed multi-clusters platform. We used 4 clusters to decode UHD video application, which cluster is composed of functional partitioned computing elements (1 DSP core and 3 hardware accelerators). The parallelizing efficiency is improved(More)
A programmable video decoding system with multi-core DSP and co-processors is presented. This system is adopted by Digital TV System on Chip (SoC) and is used for FHD High Efficiency Video Coding (HEVC) decoder under 400MHz. Using the DSP based programmable solution, we can reduce commercialization period by one year because we can parallelize algorithm(More)
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