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The soft error rate of memories is increased by high-energy particles as technology shrinks. Single-error correction codes (SEC), scrubbing techniques and interleaving schemes are the most common approaches for protecting memories from soft errors. It is essential to employ analytical models to guide the selection of interleaving distance; relying on rough(More)
— Clock line control (CLC) is proposed as a new design for testability technique which can transform a complex test generation problem into many small ones that are efficiently manageable by selectively enabling or disabling the synchronous operation of modules. A novel sequential test generation technique for the circuits with CLC scheme is also presented.(More)
This paper introduces the new failure mechanism manifested in DDR3 SDRAMs under 3× nm technology. The failure in normal cells is caused by iterative hammering accesses to a row within a refresh cycle. With the valid yet stressful access to a row, the charge in a DRAM cell leaked faster and the values of the stressed cells could not be retained. The(More)
Reliability is a critical issue for memories. Radiation particles that hit the device can cause errors in some cells, which can lead to data corruption. To avoid this problem, memories are protected with per-word error correction codes (ECCs). Typically, single-error correction and double-error detection (SEC-DED) codes are used. As technology scales,(More)