Sanghoan Chang

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The timing margin of an operating physical device suffers from crosstalk, power supply voltage fluctuation, and temperature variation among other elements. This problem is increasingly pronounced with deep-submicron technology. A conservative testing, binning and marketing policy alleviates the reliability concerns but at a loss of realizable performance of(More)
This paper presents a novel design approach for addressing the pressing problem of noise and signal integrity in high-speed circuits. The approach uses a combination of gate-level redundancy in form of a shadow circuit, exception handling, and retry to tolerate random and delay faults that are of increasing concern in modern circuits. An empirical evidence(More)
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