Sandesh Maraliga Jayaram

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A novel flash fast-locking digital phase-locked loop (DPLL) is presented and behaviorally modeled using Verilog-AMS. The DPLL operation includes two stages: (1) a novel coarse-tuning stage for frequency tracking which employs a flash algorithm leading to a thermometer code as done in flash A/D converters (ADCs) and (2) a fine-tuning stage similar to(More)
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