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CASP, Concurrent Autonomous chip self-test using <b>S</b>tored test <b>P</b>atterns, is a special kind of self-test where a system tests itself concurrently during normal operation without any downtime visible to the <b>end-user.</b> CASP consists of two ideas: 1. Storage of very thorough test patterns in non-volatile memory; and, 2. Architectural and(More)
New digital designs often include scan chains; high quality economical test is the reason. While many techniques exist for testing combinational circuitry, little attention has been paid to testing the sequential elements (latches and flip-flops). This paper presents techniques for testing latches included in either shift registers or scan chains. We show(More)
A new approach for testing the bistable elements (latches and flip-flops) in scan chain circuits is presented. In this approach, we generate test patterns that apply a checking experiment to each bistable element in the circuit while checking their response. Such tests guarantee the detection of all detectable combinational defects inside the bistable(More)
This paper introduces an assertion scheme based on the brpwprd errw amlysis for error detection in algorithms that solve dense systems of linear equations, A z = b. Unlike previous methods, this Backward Error Assertion Model is specifically designed to operate in an environment of floating point arithmetic subject to round-off errors, and it can be easily(More)