Samuel Nascimento Pagliarini

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—Defects as well as soft errors are a growing concern in micro and nanoelectronics. Multiple faults induced by single event effects are expected to be seen more often. Thus, reliability has become an important design criterion. In this context we introduce a cost-aware methodology for selective hardening of combinational logic cells. The methodology is(More)
In this work we introduce a cost-aware methodology for selective hardening of combinational logic cells, which provides a list of the most effective candidates for hardening. Two heuristics are proposed in order to define when selective hardening becomes unfeasible. The methodology and the heuristics are applied to a set of benchmark circuits using costs(More)
This paper presents a non-intrusive hybrid fault detection mechanism based on reconfigurable architectures and software-based techniques to detect transient effect faults in microprocessors. These types of faults have a major influence in microprocessors, affecting both data and control flow. In order to protect the system, an on-line checker module is(More)