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With the rising integration levels used to increase digital processing performance , there is a clear need for multiple independent on-chip supplies in order to support per-IP or block power management. Simply adding multiple off-chip DC-DC converters is not only difficult due to supply impedance concerns, but also adds cost to the platform by increasing(More)
This paper describes the embedded feedback and control system on a 90nm Itanium ®-family processor, code-named Montecito[1], that maximizes performance while staying within a target power and temperature (PT) envelope. This system, referred to as Foxton technology (FT), utilizes on-chip sensors and an embedded microcontroller to measure PT and modulate both(More)
AMD's 4+ GHz x86-64 core code-named " Piledriver " employs resonant clocking [1,2,3,4] to reduce clock distribution power up to 24% while maintaining a low clock-skew target. To support testability and robust operation at the wide range of operating frequencies required of a commercial processor, the clock system operates in two modes: direct-drive (cclk)(More)
In high-performance microprocessor cores, the on-die supply voltage seen by the transistors is non-ideal and exhibits significant fluctuations. These supply fluctuations are caused by sudden changes in the current consumed by the microprocessor in response to variations in workloads. This non-ideal supply can cause performance degradation or functional(More)
This paper presents the design and implementation of a family of high-performance soft-edge flip-flops (SEF) used in AMD products with core modules code-named “Bulldozer.” We highlight the benefits of the SEF and introduce a new method for comparing flip-flop designs in the presence of clock jitter. We describe an area-efficient(More)