Samuel Naffziger

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AMD’s 32-nm x86-64 core code-named “Piledriver” features a resonant global clock distribution to reduce clock distribution power while maintaining a low clock skew. To support a wide range of operating frequencies expected of the core, the global clock system operates in two modes: a resonant-clock (rclk) mode for energy-efficient operation over a desired(More)
In high-performance microprocessor cores, the on-die supply voltage seen by the transistors is non-ideal and exhibits significant fluctuations. These supply fluctuations are caused by sudden changes in the current consumed by the microprocessor in response to variations in workloads. This non-ideal supply can cause performance degradation or functional(More)
This paper describes the embedded feedback and control system on a 90nm Itanium-family processor, code-named Montecito[1], that maximizes performance while staying within a target power and temperature (PT) envelope. This system, referred to as Foxton technology (FT), utilizes on-chip sensors and an embedded microcontroller to measure PT and modulate both(More)
A high bandwidth critical path accumulator (1 sample/4GHz) capable of providing accurate timing margin information is reported. We present an adaptive voltage mechanism using these critical path accumulators that improves upon existing approaches by: (1) enabling replica paths to function as a statistical sample of the full set of Fmax limiting paths(More)
This paper presents the design and implementation of a family of high-performance soft-edge flip-flops (SEF) used in AMD products with core modules code-named “Bulldozer.” We highlight the benefits of the SEF and introduce a new method for comparing flip-flop designs in the presence of clock jitter. We describe an area-efficient(More)