— A low-power high-speed optical receiver in 28nm CMOS is presented. The design features a novel architecture combining a low-bandwidth TIA front-end, double-sampling technique and dynamic offset modulation. The low-bandwidth TIA increases receiver's sensitivity while adding minimal power overhead. Functionality of the receiver was validated and the design… (More)
— A low-power high-speed frequency synthesizer in 65nm CMOS is presented. The design features a novel architecture combining an LC quadrature VCO, two sample-and-holds, a phase interpolator, digital coarse-tuning and a novel quadrature frequency detection technique for fine-tuning. The system works based on injecting the rising edges of reference clock. The… (More)
We present a differential ring modulator that breaks the optical bandwidth/quality factor trade-off known to limit the speed of high-Q ring modulators. This structure maintains a constant energy in the ring to avoid pattern-dependent power droop.
With continuous demand for higher bandwidth chip-to-chip communication, signaling over wires has become extremely challenging . Optical signaling is an attractive alternative due to its small frequency-dependent loss and higher bandwidth. Recent advances in silicon photonic devices and 3D integration  have enabled them to be a viable solution for… (More)
We present a scheme for thermal stabilization of micro-ring resonator modulators through direct measurement of ring temperature using a monolithic PTAT temperature sensor. The measured temperature is used in a feedback loop to adjust the thermal tuner of the ring. The closed-loop feedback system is demonstrated to operate in presence of thermal… (More)
Modern SoC systems impose stringent requirements on on-chip clock generation and distribution. Ring-oscillator (RO) based injection-locked (IL) clocking has been used in the past  to provide a low-power, low-area and low-jitter solution. Ring-based injection-locked oscillators (ILO) can also be used to generate quadrature phases from a reference clock… (More)
—This paper presents a low-power first-order frequency synthesizer architecture suitable for high-speed on-chip clock generation. The proposed design features an architecture combining an LC quadrature voltage-controlled oscillator (VCO), two sample-and-holds, a phase interpolator, digital coarse-tuning and rotational frequency detection for fine-tuning.… (More)