Sam Sivakumar

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A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and lowCDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal–oxide–semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%,(More)
  • Sam Sivakumar
  • 16th Asia and South Pacific Design Automation…
  • 2011
Integrated circuit scaling as codified in Moore's Law has been enabled through the tremendous advances in lithographic patterning technology over multiple process generations. Optical lithography has been the mainstay of patterning technology to date. Its imminent demise has been oft proclaimed over the years but clever engineering has consistently been(More)
  • Sam Sivakumar
  • 2010 10th IEEE International Conference on Solid…
  • 2010
Lithographic scaling has been the driver for Moore Law over multiple process generations. Through the use of more advanced imaging technology and the development of advanced photoresists that are capable of finer resolution, the microelectronics industry has sustained a remarkable trend in the increase of complexity, capability and scale that is(More)
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