Learn More
—A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-CDO for high-performance dense logic is presented. Strained silicon is used to increase saturated n-type and p-type metal–oxide–semiconductor field-effect transistors (MOSFETs) drive currents by 10% and 25%,(More)
A 14nm logic technology using 2 nd-generation FinFET transistors with a novel subfin doping technique, self-aligned double patterning (SADP) for critical patterning layers, and air-gapped interconnects at performance-critical layers is described. The transistors feature rectangular fins with 8nm fin width and 42nm fin height, 4 th generation high-k metal(More)
  • Sam Sivakumar
  • 2011
Integrated circuit scaling as codified in Moore's Law has been enabled through the tremendous advances in lithographic patterning technology over multiple process generations. Optical lithography has been the mainstay of patterning technology to date. Its imminent demise has been oft proclaimed over the years but clever engineering has consistently been(More)
  • Sam Sivakumar
  • 2010
Lithographic scaling has been the driver for Moore Law over multiple process generations. Through the use of more advanced imaging technology and the development of advanced photoresists that are capable of finer resolution, the microelectronics industry has sustained a remarkable trend in the increase of complexity, capability and scale that is(More)
The regeneration frequency of cotton (Gossypium spp.) is greatly influenced by its genetic makeup and recalcitrant nature. In particular, phenolic secretion is a major problem in cotton tissue culture. The present study was carried out to develop a rapid and efficient in vitro regeneration method, without phenolic secretion, from cotyledonary node explants(More)
  • 1