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This paper presents a field programmable gate array (FPGA) implementation for a competitive Hopfield neural network (CHNN) to be used in image histogram equalization (HE). This algorithm is so computationally expensive that a viable hardware implementation is appealing provided that an efficient algorithm-to-architecture mapping can be achieved. The Xilinx(More)
This paper presents an analog layout placement tool with emphasis on Pareto front generation. In order to handle the exploding number of analog physical constraints, a new approach based on the use of a Satisfiability Modulo Theories (SMT) solver is suggested. SMT is an area concerned with checking the satisfiability of logical formulas over one or more(More)
In this paper, an automatic parallelization tool for C code, named Intelligent Automatic Parallel Detection Layer (IAPDL), is presented. It generates parallelized MPI code, and OpenMp code from the sequential code; at the loop level, to be executed on a cluster platform and multicore platform respectively. In addition to, a tool that uses a new approach to(More)
Cloud computing datacenter hosts hundreds of thousands of servers that coordinate users' tasks in order to deliver highly available computing service. These servers consist of multiple memory modules, network cards, storage disks, processors etc., each of these components while capable of failing. At such a large scale, hardware component failure is the(More)
This paper exploits one of the formal methods to generate layouts for an analog circuit, where these layouts satisfy some given analog constraints. The analog constraints are provided by the user through a text file and the used method is the Satisfiability Modulo Theories solving. After generating the layouts as valid solutions for the given constraints,(More)