Salvador Manich

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Fn this paper; two techniques to reduce the energy and the average power consumption oj the system are proposed. They are based on the fact that as lhe tesL pragresses, the detection eficiency of the pseudorundom vectocrs decreases very quickly. Many of Lhe pseudo-random vectors vi11 not detect faults in spile of consuming a signiJicant arnomt of energy(More)
A methodology to find the couple of vectors maximizing the weighted switching activity in combinational CMOS circuits under variable delay model is presented. The weighted switching activity maximization problem is shown to be equivalent to a fault testing problem on a transformed circuit. A maximum weighted switching activity is achieved by test vectors(More)
Test-pattern generators (TPGs), based on arithmetic operations, are becoming cost-effective built-in self-test solutions for circuits with embedded processors. Similar to pseudorandom TPGs, arithmetic TPGs use reseeding to reach high levels of fault coverage (FC). In this paper, we propose a method of searching for an effective reseeding strategy,(More)
units (adders, ALUs, multipliers, dividers) are essential to fault-tolerant computer designs. Some researchers based early design schemes for such units on arithmetic residue codes.1 Others proposed parity prediction schemes for the same purpose.2 These schemes compute the output operand’s parity as a function of the operator’s internal carries and of the(More)
While high-quality BIST (Built-In Self Test) based on deterministic vectors often has a prohibitive cost, pseudorandom based BIST may lead to low DC (Defects Coverage) values, requiring however very long test sequences with the corresponding energy waste and possible overheating due to extra switching activity caused by test vectors. The purpose of this(More)
Built-in self-test (BIST) strategies require the implementation of efficient test pattern generators (TPG) which allow the excitation and observation of potential faults in the circuit. Arithmetic additive TPGs (AdTPG) allow existing internal datapaths to be reused to perform this operation without a penalty in the circuit area. AdTPGs are configured by(More)
Parity prediction arithmetic operator schemes have the advantage to be compatible with data paths and memory systems checked by parity codes. Nevertheless, the basic drawback of these schemes is that they may not be fault secure for single faults, since they propagate to multiple output errors that are undetectable by the parity code. In this paper we(More)
Arithmetic additive test pattern generators (AdTPGs) are now being proposed as an alternative to linear feedback shift registers (LFSRs) because of their reduced area overhead impact. As in the case of LFSRs, the compactness of the information required in memory and the test generation time needed to achieve a specified fault coverage level (FC) have a(More)