Salvador Manich

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A methodology to find the couple of vectors maximizing the weighted switching activity in combinational CMOS circuits under variable delay model is presented. The weighted switching activity maximization problem is shown to be equivalent to a fault testing problem on a transformed circuit. A maximum weighted switching activity is achieved by test vectors(More)
Fn this paper; two techniques to reduce the energy and the average power consumption oj the system are proposed. They are based on the fact that as lhe tesL pragresses, the detection eficiency of the pseudo-rundom vectocrs decreases very quickly. Many of Lhe pseudo-random vectors vi11 not detect faults in spile of consuming a signiJicant arnomt of energy(More)
While high-quality BIST (Built-In Self Test) based on deterministic vectors often has a prohibitive cost, pseudo-random based BIST may lead to low DC (Defects Coverage) values, requiring however very long test sequences with the corresponding energy waste and possible overheating due to extra switching activity caused by test vectors. The purpose of this(More)
Parity prediction arithmetic operator schemes have the advantage to be compatible with data paths and memory systems checked by parity codes. Nevertheless, the basic drawback of these schemes is that they may not be fault secure for single faults, since they propagate to multiple output errors that are undetectable by the parity code. In this paper we(More)