Sajjad Moazeni

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A full optical chip-to-chip link is demonstrated for the first time in a wafer-scale heterogeneous platform, where the photonics and CMOS chips are 3D integrated using wafer bonding and low-parasitic capacitance thru-oxide vias (TOVs). This development platform yields 1000s of functional photonic components as well as 16M transistors per chip module. The(More)
Today's electronic photonic integration approaches involve various trade-offs between integration complexity, cost and performance, with no single approach being able to satisfy both the high-performance and low cost/complexity requirements. Luxtera's process [1] represents monolithic integration, which has low parasitics and customized photonics but slow(More)
Silicon photonics is a rapidly maturing technology, promising to realize low-cost and energy-efficient optical links for rack-to-rack, within-rack datacenter applications, and supercomputer interconnects. Recently, the possibility of implementing ultra-power-efficient silicon photonic links using an unmodified state-of-the-art 45nm SOI CMOS process has been(More)
The next generations of large-scale data-centers and supercomputers demand optical interconnects to migrate to 400G and beyond. Microring modulators in silicon-photonics VLSI chips are promising devices to meet this demand due to their energy efficiency and compatibility with dense wavelength division multiplexed chip-to-chip optical I/O. Higher order pulse(More)
System-level driven electronic–photonic codesign is the key to improving the bandwidth density and energy efficiency for high-speed silicon photonic links. In many data-communication scenarios, optical link power is dominated by its transmitter side including the laser source. In this paper, we propose a comprehensive co-optimization framework for(More)
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