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A CMOS ADC architecture is presented that combines pipelined low pass ADCs with time interleaving to obtain sampling frequencies in the 3 to 6 GHz range with bandwidths of 1.5 to 3 GHz and 10-12 bits of resolution. The schematic design and performance simulations are included for a 180 nm CMOS process. The Time Interleaved Pipelined (TIP) ADC samples at 3.2(More)
A new unity gain bu®er architecture is presented for on-chip CMOS mixed signal applications. The proposed two-stage common source active load (CSAL) bu®er with source feedback o®ers improved performance compared to previously published source follower and source-coupled di®erential-pair-based unity gain bu®ers. A 90-nm CMOS design (Vdd equals 1.2V) of the(More)
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