Saihua Lin

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In this paper, we propose a new capacitive boosted buffer technique that can be used in high speed interconnect for ultra-dynamic voltage scaling (UDVS) application with the process variation effect mitigated. The circuit is simple and fully compatible with digital CMOS technology. Implemented in a standard 0.18 μm CMOS technology, the circuit is shown(More)
In this paper, a novel soft-error-tolerant latch and a novel soft-error-tolerant flip-flop are presented for multiple VDD circuit design. By utilizing local redundancy, the latch and the flip-flop can recover from soft errors caused by cosmic rays and particle strikes. By using output feedback, implicit pulsed clock, and conditional discharged techniques,(More)
An efficient method to analyze the transient response of distributed RLC interconnects is proposed in this paper. After introducing numeral discrete capacitance and inductance, Norton theorem is applied to generate a reduced-order equivalent circuit, and finally a linear-time-complexity algorithm is then achieved to solve the distributed RLC interconnect.(More)
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