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A 1.5-V 100-mA CMOS low-dropout regulator based on a novel structure, with a double pole-zero cancellation scheme and a linearly operated power PMOS transistor at dropout to enhance the loop-gain response, is presented. The circuit realization is well-studied and developed with respect to the loop-gain response, the transient response, the output noise and(More)
This paper presents a high PSRR full on-chip and area efficient low dropout voltage regulator (LDO), exploiting the nested miller compensation technique with active capacitor (NMCAC) to eliminate the external capacitor. A novel technique is used to boost the important characteristic for wireless applications regulators PSRR. The idea is applied to stabilize(More)
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