Sadahiro Tani

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The random logic portion of an MOS LSI chip intended mainly for a calculator is constructed of an array of MOS complex gates, each composed of an MOS ratioless circuit with a multi-phase clocking system, and occupies ordinarily a considerable part of chip area. In this paper, a layout system for this portion of an LSI is described, which is constructed on(More)
This paper discusses interconnect capacitance extraction for system LCD circuits, where coupling capacitance is much significant since a ground plane locates far away unlike LSI interconnects. We focus on a pattern matching method with interpolation to implement an accurate and efficient capacitance extraction system, and present good implementations that(More)
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