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Except where reference is made to the work of others, the work described in this thesis is my own or was done in collaboration with my advisory committee. This thesis does not include proprietary or classified information. Permission is granted to Auburn University to make copies of this thesis at its discretion, upon the request of individuals or(More)
– We present an embedded processor based approach for Built-In Self-Test (BIST) and diagnosis of pro-grammable logic and memory resources in Field Programmable Gate Arrays (FPGAs). The resources under test include the programmable logic blocks (PLBs), large random access memories (RAMs), and digital signal processors (DSPs) in all of their modes of(More)
We present a Built-In Self-Test (BIST) approach for testing and diagnosing the programmable logic and memory resources in Xilinx Virtex-4 series Field Programmable Gate Arrays (FPGAs). The resources under test include the programmable logic blocks (PLBs) and block random access memories (RAMs) in all of their modes of operation. The BIST architecture and(More)
Built-In Self-Test (BIST), as the name suggests is a technique in which the circuit is capable of testing itself. This paper presents two techniques: Linear Feedback Shift Register (LFSR) and Cellular Automata (CA), used for test pattern generation and test response analysis in a typical BIST circuit. Both LFSR and CA are analyzed based on their(More)
Antibiotics for presumed small intestinal bacterial overgrowth have been shown to improve irritable bowel syndrome symptoms in at least 40 % of subjects. A lactulose breath test for small intestinal bacterial overgrowth has been used to select patients who will respond. However, its predictive value, using the classic definition of a positive lactulose(More)
OBJECTIVE: Write a test pattern generation program using the PODEM algorithm. ABSTRACT: PODEM (Path-Oriented Decision Making) is an Automatic Test Pattern Generation (ATPG) algorithm which was created to overcome the inability of D-Algorithm (D-ALG) to generate test vectors for circuits involving Error Correction and Translation. The aim of this project is(More)
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