Sabrina E. Kemeny

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The yeast S. cerevisiae is a central model organism in eukaryotic cell studies and a major component in many food and biotechnological industrial processes. However, the wide knowledge regarding genetics and molecular biology of S. cerevisiae is based on an extremely narrow range of strains. Studies of natural populations of S. cerevisiae, not associated(More)
A new CMOS-based image sensor that is intrinsically compatible with onchip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 pm p-well CMOS process, and consists of a 128 x 128 array of 40 pm x 40 pm(More)
The recent development of the CMOS active pixel sensor (APS) has, for the first time, pennitted large scale in­ tegration of supporting circuitry and smart camera functions on the same chip as a high-performance image sensor. This paper reports on the demonstration of a new 128 x 128 CMOS APS with programmable multiresolution readout capability. By placing(More)
A 128x128 element CMOS active pixel image sensor (APS) with on-chip timing, control, and signal chain electronics has been designed, fabricated and tested. The chip is implemented in 1.2 pm nwell process with a 19.2 tm pixel pitch. The sensor uses a photodiode-type CMOS APS pixel with in-pixel source follower, row selection and reset transistors. The sensor(More)
The recent development of the CMOS active pixel sensor (APS) has, for the first time, permitted large scale integration of supporting circuitry and smart camera functions on the same chip as a high-performance image sensor. This paper reports on the demonstration of a new 128 128 CMOS APS with programmable multiresolution readout capability. By placing(More)
CMOS active pixel sensors (APS) allow the flexibility of placing signal processing circuitry on the imaging focal plane. The multiresolution CMOS APS can perform block averaging on-chip to eliminate the off-chip software intensive image processing. This 128 x 128 APS array can be read out at any user-defined resolution by configuring a set of digital shift(More)
A family of CMOS-based active pixel image sensors (APS’s) that are inherently compatible with the integration of onchip signal processing circuitry is reported. The image sensors were fabricated using commercially available 2m CMOS processes and both p-well and n-well implementations were explored. The arrays feature random access, 5-V operation and(More)
An update on research activities at Columbia University in the area of focal-plane image processing is presented. Two thrust areas have been pursued: image reorganization for image compression and image half-toning. The image reorganization processor is an integration of a 256 x 256 frame-transfer CCD imager with CCD-based circuitry for pixel data(More)
The first integration of a 24 x 25 array of processors for high speed optimal path planning is reported. Based on programmed terrain costs (traversal time), the IC determines, in parallel, the fastest routes from a selected starting point(s) to all other points on a given tcrrain. The chip has hQen successfully tested at a 7 MHz clock frequency, with(More)