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1-bit full adder is a very great part in the design of application particular integrated circuits. Power consumption is one of the most significant parameters of full adders. Therefore reducing power consumption in full adders is very important in low power circuits. In this paper, we propose two new structures of hybrid full adders. The first full adder(More)
A new three stage low-noise, high-gain operational amplifier (Op-Amp) is proposed in this paper. Design strategies are discussed for minimizing noise and increasing gain. Multipath nested Miller compensation used for three stage operational amplifier. The circuit is designed in the 0.18μm CMOS technology. The HSPICE software was used for simulation.(More)
A cell-based analytical percolation model recently proposed for the dielectric breakdown (BD) of high-K stack gate dielectrics is reformulated in terms of competing local percolation paths. The model is equivalent to kinetic Monte Carlo implementation of percolation and it is shown to be consistent with large sample size statistical data. This is a(More)
—In this paper a high performance CMOS operational amplifier (op amp) using dynamic threshold voltage MOSFET (DTMOS) technique is presented. A two stage operational amplifier is designed and simulated using 0.18 µm CMOS technology. The performed simulation results show an input-referred noise of 490.82 nV/√Hz at 100 Hz, and a power consumption of 38.53 µW(More)
All oscillators are periodically time varying systems, so to accurate phase noise calculation and simulation, time varying model should be considered. Phase noise is an important characteristic of oscillator design. It defined as the spectral density of the oscillator spectrum at an offset from the center frequency of the oscillator relative to the power of(More)
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