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16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS
TLDR
A variation-tolerant all-digital PUF array targeted for on-die generation of 100% stable, device-specific, high-entropy keys is fabricated in 22nm tri-gate high-κ metal-gate CMOS. Expand
2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors
TLDR
This paper describes an all-digital PVT-variation tolerant true-random number generator (TRNG), fabricated in 45 nm high-k/metal-gate CMOS, targeted for on-die entropy generation in high-performance microprocessors. Expand
340 mV–1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS
TLDR
This paper describes an on-die lightweight nanoAES hardware accelerator, fabricated in 22 nm tri-gate high-k/metal-gate CMOS, targeted for ultra-low power symmetric-key encryption and decryption on mobile SOCs. Expand
A 4 GHz 130 nm address generation unit with 32-bit sparse-tree adder core
TLDR
This paper describes a 32-bit Address Generation Unit (AGU) designed for 4 GHz operation in 1.2 V, 130 nm technology with 20% delay reduction, 80% lower interconnect density and a low (1%) active energy leakage component. Expand
A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS
TLDR
This paper describes a full-entropy 128-b key generation platform based on a 1024-b hybrid physically unclonable function (PUF) array fabricated in 14-nm trigate high-k/metal-gate CMOS. Expand
53Gbps native GF(24)2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45nm high-performance microprocessors
TLDR
An on-die, reconfigurable AES encrypt/decrypt hardware accelerator is fabricated in 45nm CMOS, targeted for content-protection in high-performance microprocessors. Expand
An improved unified scalable radix-2 Montgomery multiplier
TLDR
This paper describes an improved version of the Tenca-Koc unified scalable radix-2 Montgomery multiplier with half the latency for small and moderate precision operands and half the queue memory requirement. Expand
$\mu $ RNG: A 300–950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS
TLDR
This paper describes μRNG, an ultra-lightweight all-digital full-entropy true-random number generator (TRNG), fabricated in 14 nm high-k/metal-gate FinFET CMOS, targeted for on-die generation of cryptographic keys in energy-constrained IoT and wearable platforms. Expand
A 4-GHz 300-mW 64-bit integer execution ALU with dual supply voltages in 90-nm CMOS
TLDR
This paper describes a single-cycle 64-bit integer execution ALU fabricated in 90-nm dual-Vt CMOS technology, operating at 4 GHz with a 32-bit mode frequency of 7 GHz (measured at 1.3 V, 25/spl deg/ C). Expand
53 Gbps Native ${\rm GF}(2 ^{4}) ^{2}$ Composite-Field AES-Encrypt/Decrypt Accelerator for Content-Protection in 45 nm High-Performance Microprocessors
TLDR
This paper describes an on-die, reconfigurable AES encrypt/decrypt hardware accelerator fabricated in 45 nm CMOS, targeted for content-protection in high-performance microprocessors. Expand
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