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Charge pump with perfect current matching characteristics in phase-locked loops
Conventional CMOS charge pump circuits have some current mismatching characteristics. The current mismatch of the charge pump in the PLLs generates a phase offset, which increases spurs in the PLLExpand
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A New Auto Exposure and Auto White-Balance Algorithm to Detect High Dynamic Range Conditions Using CMOS Technology
paper proposes a new auto-exposure and auto white-balance algorithm that can accurately detect high-contrast lighting conditions and improve the dynamic range of output images for a camera system.Expand
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A New Auto Exposure System to Detect High Dynamic Range Conditions Using CMOS Technology
TLDR
This paper proposes a new auto-exposure algorithm that can accurately detect high-contrast lighting conditions and improve the dynamic range of output images for a camera system. Expand
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Improved field emission stability of thin multiwalled carbon nanotube emitters.
The improved field emission stability of thin multiwalled carbon nanotube (thin-MWCNT) emitters using a tip sonication process has been investigated. The thin-MWCNTs showed short lengths and manyExpand
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Modeling and Testing of Faults in TCAMs
TLDR
This paper proposes novel fault models for ternary content addressable memories (TCAMs) regarding both physical defects and functional fault models. Expand
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Image enhancement using a fusion framework of histogram equalization and laplacian pyramid
TLDR
We propose an image enhancement method based on a modified Laplacian pyramid framework that decomposes an image into band-pass images to improve both the global contrast and local information. Expand
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A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology
TLDR
This paper presents an all digital delay-locked loop (DLL) which achieves low jitter and stable duty cycle correction (DCC) operation. Expand
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The v2.0+EDR Bluetooth SOC architecture for multimedia
TLDR
This paper presents a Bluetooth system on chip (SOC) architecture for multimedia applications. Expand
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A 32-bit carry lookahead adder using dual-path all-N logic
TLDR
We have developed dual path all-N logic (DPANL) and applied it to 32-bit adder design for higher performance. Expand
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A CMOS image sensor (CIS) architecture with low power motion detection for portable security camera applications
TLDR
This paper presents a low power motion detection algorithm and its system architecture. Expand
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