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- Yih Wang, Hong Jo Ahn, +14 authors M. Bohr
- IEEE Journal of Solid-State Circuits
- 2008

A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakageâ€¦ (More)

- M.W. Newman, Susendar Muthukumar, +10 authors J. M. Swan
- 56th Electronic Components and Technologyâ€¦
- 2006

3D die-stacking (Tanida et al, 2003; Hara et al, 2005) and wafer-stacking (Morrow et al, 2004) integration have recently been demonstrated using copper (Cu) interconnections and through silicon viaâ€¦ (More)

- S. H. Kulkarni, S. Pae, +7 authors Kevin Zhang
- 2012 Symposium on VLSI Technology (VLSIT)
- 2012

A 1 k-bit high-density OTP (One Time Programmable)-ROM array featuring a new anti-fuse memory is presented using 32nm high-k (HK) and metal-gate (MG) CMOS process. Our 32nm HK+MG SOC processâ€¦ (More)

- S. H. Kulkarni, Z. Chen, B. Srinivasan, B. Pedersen, U. Bhattacharya, Kai Zhang
- 2015 Symposium on VLSI Circuits (VLSI Circuits)
- 2015

This work introduces the first high-volume manufacturable metal-fuse technology in a 22nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 16.4Î¼m2 1T1R bit cell is presentedâ€¦ (More)

- Jerry Chang, Jim Shoemaker, +11 authors Stefan Rusu
- 2004 IEEE International Solid-State Circuitsâ€¦
- 2004

The 18-way set-associative, single-ported 9 MB cache for the Itanium/spl reg/2 processor, presented in this paper, uses 210 identical 48 kB sub-arrays with a 2.21 /spl mu/m/sup 2/ cell in a 0.13 /splâ€¦ (More)

- S. H. Kulkarni, Daniel Sukumar
- Int. J. Math. Mathematical Sciences
- 2005

We prove by elementary methods the following generalization of a theorem due to Gleason, Kahane, and Å»elazko. Let A be a real algebra with unit 1 such that the spectrum of every element in A isâ€¦ (More)

- Jerry Chang, Stefan Rusu, +10 authors S. H. Kulkarni
- IEEE Journal of Solid-State Circuits
- 2005

The 18-way set-associative, single-ported 9 MB cache for the Itanium 2 processor uses 210 identical 48-kB sub-arrays with a 2.21-/spl mu/m/sup 2/ cell in a 130-nm 6-metal technology. The processorâ€¦ (More)

- Z. Chen, S. H. Kulkarni, V. E. Dorgan, U. Bhattacharya, Kai Zhang
- 2016 IEEE Symposium on VLSI Circuits (VLSIâ€¦
- 2016

This work introduces the first high-volume manufacturable (HVM) metal-fuse technology in a 14nm tri-gate high-k metal-gate CMOS process. A high-density array featuring a 0.9Î¼m2 1T1R bit cell and bitâ€¦ (More)

- S. H. Kulkarni
- The American Mathematical Monthly
- 2004

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