• Publications
  • Influence
Dissecting Ponzi schemes on Ethereum: identification, analysis, and impact
TLDR
We present a comprehensive survey of Ponzi schemes on Ethereum, analysing their behaviour and their impact from various viewpoints. Expand
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/spl times/pipes Lite: a synthesis oriented design library for networks on chips
TLDR
The limited scalability of current bus topologies for systems on chips (SoCs) dictates the adoption of networks on Chips (NoCs) as a scalable interconnection scheme. Expand
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Designing Application-Specific Networks on Chips with Floorplan Information
TLDR
We present a floorplan aware design method that considers the wiring complexity of the NoC during the topology synthesis process that automates the synthesis of such application-specific NoC architectures. Expand
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Assessing Task Migration Impact on Embedded Soft Real-Time Streaming Multimedia Applications
TLDR
In this paper we first present a middleware infrastructure supporting dynamic task allocation for NUMA architectures. Expand
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A Feedback-Based Approach to DVFS in Data-Flow Applications
TLDR
In this paper, we present a control theoretic approach to dynamic voltage/frequency scaling for data-flow models of computations mapped to multiprocessor systems-on-chip architectures. Expand
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State-of-the-Art in Group Recommendation and New Approaches for Automatic Identification of Groups
TLDR
We present a survey of the state-of-the-art in group recommendation, focusing on the type of group each system aims to. Expand
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Group Recommendation with Automatic Identification of Users Communities
TLDR
This paper describes an algorithm that detects groups of users whose preferences are similar and predicts recommendations for such groups through a modularity-based Community Detection algorithm. Expand
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Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors
TLDR
We address the design issue of synthesizing the most power efficient NoC interconnect for CMPs, providing guaranteed optimum throughput and predictable performance for any application to be executed on the CMP. Expand
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Area and Power Modeling for Networks-on-Chip with Layout Awareness
TLDR
We propose an NoC modeling methodology which takes advantage of the designer’s knowledge of the target architecture, and propose strategies for coefficient characterization which have different tradeoffs in terms of accuracy and of modeling activity effort. Expand
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