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Dissecting Ponzi schemes on Ethereum: identification, analysis, and impact
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Designing Application-Specific Networks on Chips with Floorplan Information
TLDR
This work presents a floorplan aware design method that considers the wiring complexity of the NoC during the topology synthesis process, and incorporates mechanisms to prevent deadlocks during routing, which is critical for proper operation of NoCs.
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State-of-the-Art in Group Recommendation and New Approaches for Automatic Identification of Groups
TLDR
This chapter will present a survey of the state-of-the-art in group recommendation, focusing on the type of group each system aims to, able to adapt to technological constraints (e.g., bandwidth limitations).
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/spl times/pipes Lite: a synthesis oriented design library for networks on chips
The limited scalability of current bus topologies for systems on chips (SoCs) dictates the adoption of networks on chips (NoCs) as a scalable interconnection scheme. Current SoCs are highly…
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A Feedback-Based Approach to DVFS in Data-Flow Applications
TLDR
A control theoretic approach to dynamic voltage/frequency scaling for data-flow models of computations mapped to multiprocessor systems-on-chip architectures is presented and nonlinear control approaches to deal with general streaming applications containing both pipeline and parallel stages are discussed.
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Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors
TLDR
This paper addresses the important design issue of synthesizing the most power efficient NoC interconnect for CMPs, providing guaranteed optimum throughput and predictable performance for any application to be executed on the CMP.
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Assessing Task Migration Impact on Embedded Soft Real-Time Streaming Multimedia Applications
TLDR
A middleware infrastructure supporting dynamic task allocation for NUMA architectures is presented and an extensive characterization of its impact on multimedia soft real-time applications using a software FM Radio benchmark is performed.
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Area and Power Modeling for Networks-on-Chip with Layout Awareness
TLDR
This work presents a flow to devise analytical models of area occupation and power consumption of NoC switches, and proposes strategies for coefficient characterization which have different tradeoffs in terms of accuracy and of modeling activity effort.
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Contrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness
TLDR
This paper brings crossbar and NoC designs to the chip layout level in order to highlight the respective strengths and weaknesses in terms of performance, area and power, keeping an eye on future scalability.
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Group Recommendation with Automatic Identification of Users Communities
TLDR
An algorithm is described that detects groups of users whose preferences are similar and predicts recommendations for such groups, making it possible for a content provider to explore the trade off between the level of personalization of the recommendations and the number of channels.
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