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VHDL implementation of an optimized 8-point FFT/IFFT processor in pipeline architecture for OFDM systems
TLDR
An optimized implementation of the 8-point FFT processor with radix-2 algorithm in R2MDC architecture is presented in this paper. Expand
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Real-time parallel implementation of Pulse-Doppler radar signal processing chain on a massively parallel machine based on multi-core DSP and Serial RapidIO interconnect
TLDR
A massively parallel machine has been developed in this paper to implement a Pulse-Doppler radar signal processing chain in real-time fashion. Expand
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Low power and fast DCT architecture using multiplier-less method
TLDR
In this paper, a low power and fast DCT (Discrete Cosine Transform) using multiplier-less method is presented with a new modified FGA (Flow-Graph Algorithm), which is derived from our previously presented FGA of DCT based on Loeffler algorithm. Expand
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Improved implementation of a modified Discrete Cosine Transform on low-cost FPGA
TLDR
In this paper, Discrete Cosine Transform hardware implementations are performed using two different modified Loeffler algorithms and are compared to the original one. Expand
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Efficient parallelization of GMM background subtraction algorithm on a multi-core platform for moving objects detection
TLDR
In this paper, we propose an efficient multi-threading parallelization of GMM on a 16-cores Intel node using the OpenMP framework. Expand
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Performance and scalability improvement of GMM background segmentation algorithm on multi-core parallel platforms
TLDR
We propose some efficient tips to improve the performance and the scalability of Gaussian Mixture Model background subtraction using the OpenMP framework. Expand
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Single Core SIMD Parallelization of GMM Background Subtraction Algorithm for Vehicles Detection
TLDR
In this paper, we propose an efficient data vectorization of GMM on two different Intel architectures using the SSE2 vector instructions. Expand
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Design optimization of the quantization and a pipelined 2D-DCT for real-time applications
TLDR
In this paper, in addition to the hardware implementation on an FPGA, an extended optimization has been performed by merging the multiplications in the quantization block without having an impact on the image quality. Expand
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Efficient architecture for direct 8 × 8 2D DCT computations with earlier zigzag ordering
TLDR
In this paper, we propose a low complexity architecture for direct 2D DCT zigzag reordering and quantization merged architecture, which respects the real time HDTV video requirements with low power consumption. Expand
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Instruction scheduling heuristic for an efficient FFT in VLIW processors with balanced resource usage
TLDR
We propose a new FFT implementation on high-end very long instruction word (VLIW) digital signal processors (DSP), which presents improved performance in terms of clock cycles due to the resulting low-level resource balance and to the reduced memory accesses of twiddle factors. Expand
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