S. Balachandran

We propose a new a priori interconnect and wirelength estimation methodology for island style field programmable gate arrays (FPGAs). Expand

This paper proposes a new mathematical model to approximate the HPWL cost function that can be used in analytical placers. Expand

We propose an algorithm, Fast-SL, which surmounts the computational complexity of previous approaches by iteratively reducing the search space for synthetic lethals, resulting in a substantial reduction in running time, even for higher order synthetic lethal. Expand

We propose a new a priori interconnect and wirelength estimation methodology for island style field programmable gate arrays (FPGAs). Expand

In modern CMPs, Last Level Cache (LLC) is shared among cores for better utilization. Expand

Heterogeneous Multiprocessors (HMPs) are popular due to their energy efficiency over Symmetric Multicore Processors (SMPs). Expand

We present a new approximation scheme which uses a non-recursive approximation to the max function. Expand

We propose a uniform reporting metric based on comparing the estimates produced with the results of an actual detailed router on both local and global levels. Expand

We introduce a new methodology, fGREP, for ultra-fast estimation of routing demands for placed circuits on FPGAs. Expand