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A Product-Level Reliability Estimator (PLRE), which calculates failure rate of a chip as a function of use conditions, has been developed for the first time. Major wafer-level failure mechanisms such as Time-Dependent Dielectric Breakdown (TDDB) and Electro Migration (EM) are included. By applying PLRE to the product with advanced CMOS technology,(More)
A collaborative framework is presented to address the reliability challenges faced in a fabless-foundry environment. Examples are given to show the effectiveness of this framework for both infant mortality and long-term reliability risk. Through design-for-reliability, optimum process standardization and selective customization, defect density reduction and(More)
Stacked die packaging has been gaining traction in recent years due to cost and manufacturing issues associated transistor scaling. 3D die stacking architecture with through silicon vias offers a unique combination of low power and high bandwidth per watt without increasing the cost significantly. For Xilinx's FPGAs (Field Programmable Gate Array), due to(More)
Product-level Reliability Estimator (PLRE) has been built for 20nm technology product. With PLRE, users can estimate failure rate of the chip with various use conditions. EDA tools are used to estimate each block's reliability budget, in terms of effective area for TDDB and effective number for EM which are to be used in building PLRE. Budget-based(More)
In this paper, we report the presence of B10 based on SIMS analysis in SRAM arrays in the 90nm to 45nm technology nodes. The physical presence of B10 correlated very well with the thermal neutron soft error rate (SER) sensitivity of SRAM cells. This result confirmed that without BPSG layer in advanced Si technologies, there is still a high possibility of(More)
As the size and complexity of the designs grows larger, Field Programmable Gate Array (FPGA) based design solutions are becoming more dominant in system designs due to their ability to offer higher logic capacity and more on chip resources. FPGA based design solutions that offer higher capacity and higher bandwidth with low latency and power can provide(More)
Eutectic PbSn solder joints assembled with CuSOP and ENEPIG surface finished substrates were tested at three different temperatures and input currents to predict EM life. Estimated EM life of CuSOP with PbSn solder system is 3 to 4 X longer than that of ENEPIG surface finish. Both EM failures in solder bumps are caused by void formation at the current(More)
Assembly of stacked die side by side on a passive interposer enables high-bandwidth connectivity between multiple die by providing a significantly large number of die to die connections that otherwise are not possible in a multi-chip-module (MCM) configuration. It also provides much lower latency and consumes dramatically lower power than either the(More)
This paper presents results for assembly and reliability evaluations performed while developing a first of its kind heterogeneous 2.5D HiCTE Ceramic Field Programmable Gate Array (FPGA) package. The heterogeneous device discussed here is a three dimensionally stacked FPGA device integrated with a 28G Transceiver die using a passive interposer. Several(More)
We conducted TDDB test and Vrdb test on two different stressed cap layer (CESL, contact-etch-stop-layer) processes as a part of evaluation of 40 nm deep submicron technology for pMOS. Similar Weibull distributions including shape factor, temperature and voltage acceleration factors, were observed in TDDB between two processes. However, Vrdb results present(More)