S. Srinivasan

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A novel architecture suitable for FPGA/ASIC implementation of a video scalar is presented. The scheme proposed here results in enormous savings of memory normally required, without compromising on the image quality. In the present work, SVGA compatible video sequence is scaled up to XGA format. The up scaling operation for a video sequence is carried out by(More)
This paper presents a novel architecture for the implementation of a 2-D discrete wavelet transform (DWT) for image compression. The architecture is designed for lifting based DWT. The advantages of the lifting based DWT and its inverse, IDWT, over the convolution based scheme are lower computational complexity and reduced memory requirements. Hence, the(More)
This paper presents architectures and scheduling algorithms for the 2-D Discrete Wavelet Transform (DWT) and the Inverse Discrete Wavelet Transform (IDWT) using 9/7-tap filter banks based on the Non-expansive Symmetric Extension (NSE) scheme that reduces distortion at boundaries of reconstructed image. The hardware has been implemented for image blocks of(More)
A novel implementation of Two Dimensional Discrete Cosine Transform (2D-DCT) using Embedded Programmable Logic Devices (EPLDs) has been proposed in this paper. The key feature of this scheme is that it’s architecture is regular, linear, pipelined and it fits into just four numbers of commercially available EPLDs. It is capable of processing images of size(More)
OBJECTIVES New-onset diabetes mellitus (DM) may herald pancreatic cancer (PaC). We determined whether changes in body weight distinguished PaC-associated DM (PaCDM) from type 2 DM. METHODS Among Olmsted County residents, we identified 29 PaCDM and 43 type 2 DM subjects who had serial fasting blood glucose measurements, new-onset DM, and no cancer-specific(More)
In this paper, a new high-speed VLSI architecture for decoding Reed-Solomon codes with the Berlekamp-Massey algorithm is presented. The proposed scheme uses the fully folded systolic architecture in which a single array of processors, computes both the error-locator and the error-evaluator polynomials. The proposed scheme utilizes the folding property of(More)