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As microprocessors enter the highly multi-core/multi-threaded era, higher density, lower latency embedded memory will be required to meet cache design needs. This paper describes a 500 MHz random cycle silicon on insulator (SOI) embedded DRAM macro which features a three-transistor micro sense amplifier, realizing significant performance gains over(More)
Chip performance, power, noise, and clock synchronization are becoming formidable challenges as microprocessor performance moves into the GHz regime and beyond. Interlocked pipelined CMOS (IPCMOS), an asynchronous clocking technique, helps address these challenges. This paper shows how a typical block (e.g., Block D) is interlocked with all the blocks with(More)
An approach is described for determining the hot-electron-limited voltages for silicon MOSFET's of small dimensions. The approach was followed in determining the room-temperature and the 77 K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 µm. The substrate hot-electron limits were determined empirically from(More)
Graphical techniques for analysis of the stability and soft error rate (SER) of static RAM cells have been developed. These techniques include important transient effects and make readily visible the impact of variations in design approaches and parametrics. The techniques are illustrated with application to a high-speed 64K NMOS RAM and comparative cases.(More)
Describes a study in which a PLA-based macro design of a small processor is carried out in the same technology as the original `random' logic design of the same processor. The objectives of the study were to determine gains or losses in `technology utilization' when a PLA-based approach is used to replace the more conventional `random' logic approach. The(More)
For pt. II see ibid., vol.SC14, no.2, p.247 (1979). Logic circuits were designed and fabricated in a 1 /spl mu/m silicon-gate MOSFET technology. First, conventional random logic chip images using the largely one-dimensional `Weinberger' layout are examined. The image is able to provide chips with an average circuit delay of 3 ns at the 8000 circuit level of(More)
In this paper, a hierarchical differential sense amplifier for fast, low power DRAM arrays in logic-based eDRAM technology that operates with large parameter variations is described. Unique features of the hierarchical sense amplifier include its short local bit lines and a local half sense amplifier p device latch that is connected by a switch to a global(More)
For pt.III see ibid., vol.SC14, no.2, p.255 (1979). An approach is described for determining the hot-electron-limited voltages for silicon MOSFETs of small dimensions. The approach was followed in determining the room-temperature and the 77K hot-electron-limited voltages for a device designed to have a minimum channel length of 1 /spl mu/m. The substrate(More)
On-chip test circuitry which provides 8-bit-deep ECL-level patterns to 12 input pads of a 512Kb CMOS ECL SRAM at cycle times as fast as 1.4 ns has been built in a 0.8¿m CMOS technology with L<inf>eff</inf> = 0.5¿m. A unique approach for synchronizing the input signals to the chip-select signal in order to provide optimum set-up time and data-valid window is(More)
An approach is described for determining the hot-electron-limited voltages for silicon IGFET's of small dimensions. The approach was followed in determining the room-temperature and the 77&#176;K hot-electron-limited voltages for a device designed to have a minimum channel length of one micron. The substrate-hot-electron limits were determined from a(More)