S. Rumler

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In this paper we pnrent a new approach to the scheduling of behaviorol VHDL descriptions for control-flow dominated applications containing a large number of nested conditionds and data dependent loops. The proposed algorithm is able to schedule and n-schedule descriptions for optimization subject to variour cost junctions. The timing of the .1/O signals(More)
We present a VHDL .wbsetfor high-levet synthesis allowing a j7exible timing specification of the circuit interface such that the optimization potential of classical scheduling and allocation techniques can be fully used. On the other hand, thealgorithmic circuit specification can be validated by a conventional VHDL simulator, if the description style(More)
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