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In this paper, Bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized HK film stack in the early development phase exhibited pre-existing traps and large amount of hysteresis that was consistent with literature. The optimized and(More)
C. Prasad, M. Agostinelli, C. Auth, M. Brazier, R. Chau, G. Dewey, T. Ghani, M. Hattendorf, J. Hicks, J. Jopling, J. Kavalieros, R. Kotlyar, M. Kuhn, K. Kuhn, J. Maiz, B. McIntyre, M. Metz, K. Mistry, S. Pae, W. Rachmady, S. Ramey, A. Roskowski, J. Sandford, C. Thomas, C. Wiegand, J. Wiedemer, Logic Quality & Reliability, Logic Technology Development ,(More)
OBJECTIVE To determine whether job-related stress is associated with alterations in pro- and anti-atherogenic inflammatory mediators among law enforcement officers. METHODS Markers of vascular inflammation and the self-reported stress measures of perceived stress, vital exhaustion, job strain, effort-reward imbalance, and social support were compared(More)
In this paper, the reliability of the vertical drain NMOS (VDNMOS) device structure has been evaluated for a state of the art CMOS process. In past technologies, reliability was restricted by hot carrier degradation effects. With technology scaling, gate oxide wear-out has become the reliability limiter. A new VDNMOS oxide wear-out model has been developed(More)
Tremendous amounts of wafer level reliability testing is required to support transistor technology development efforts. Conventional testing takes considerable time which severely limits reliability organizations. We present two approaches that help increase data velocity for wafer level reliability measurements and discuss their current limitations.
Charge Pumping (CP) has historically been a widely utilized tool to study reliability-limiting interface and near interface trapping centers in Metal-Oxide-Semiconductor Field-Effect-Transistors (MOSFETs). However, conventional CP methods are not effective for modern highly scaled devices due to high gate leakage current to CP current ratios. Fortunately, a(More)
As tri-gate transistor technologies continue to scale to smaller dimensions, a variety of aging mechanisms become important to include in models to accurately predict end-of-life transistor performance. Traditional aging effects such as BTI and hot carrier continue to play a role. However, modeling these mechanisms becomes more complicated with the addition(More)
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