S. R. Chowdhury

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The necessity for high speed computation has motivated the development of a high performance processor for floating point computations. In this paper we examine, changes in the performance of a floating-point operation with respect to the number of processing units in case of a super scalar architecture. The prototype of the processors has been realized and(More)
This paper presents post layout simulations of a new 8T full adder cell using a new 3T XOR gate implemented by pMOS transistors only. This proposed design operates efficiently in super threshold region to achieve ultra low power and hence reduced power-delay product (PDP). The proposed design demonstrates its superiority against existing adder in terms of(More)
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