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A 16384-bit charge-coupled device (CCD) memory has been developed for mass storage memory system application where moderate latency, high data rate and low system cost are required. The chip measures only 3.45/spl times/4.29 mm/SUP 2/ (136/spl times/169 mil/SUP 2/), fits a standard 16-pin package, and is organized as four separate shift registers of 4096(More)
We have developed an advanced CMOS technology for application in fast SRAMS, non-volatile memory, microprocessor and logic circuits. Features of the 1.2µm (gate and contact) double-level-poly, double-level-metal technology include a twin-well CMOS [1] structure in n- or p-type starting material, SILO isolation [2] for high packing density, 250 A thick(More)
To ensure maximum tool utilization in high volume semiconductor manufacturing, multiple etch recipes may be implemented on a given etch chamber configuration. Due to the increased process complexity required for 0.25 /spl mu/m semiconductor fabrication, residual effects in chambers and interaction between etch recipes can change individual etch process(More)
A 16,384-bit charge-coupled device (CCD) memory has been developed for mass storage memory system application where moderate latency, high data rate and low system cost are required. The chip measures only 136 &#215; 169 mil<sup>2</sup>to fit a standard 16-pin package and is organized as four separate shift registers of 4096 bits. A condensed(More)
Manufacturing issues concerning 0.25 micron CMOS technologies including devices for high performance processor, dense SRAM, and low power circuits are discussed. Tradeoffs between performance, cost, and statistical effects such as gate length and Vt control are presented. Requirements for future technologies are identified to improve maturity prior to(More)
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