S. Maerkovich

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A low power and very low area 10-bit 220MS/s SAR ADC is presented. The ADC employs a redundancy scheme that relaxes the DAC settling requirement and enables high sample rates, as well as a digital metastability identification and correction algorithm that exploits the redundancy as an error-correction code. The proposed ADC was implemented in CMOS 65nm, and(More)
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