We don’t have enough information about this author to calculate their statistics. If you think this is an error let us know.
Learn More
Scaling down of the CMOS technology requires ultra thin oxide to meet the scaling of gate length. Gate oxide reliability becomes important as the gate oxide thickness is reduced. Tunneling current that flow through the thin oxide will cause an increase of the off-state current leakage and unnecessary power dissipation. In this study, probing is performed(More)
As the device becomes smaller, overlay accuracy requirement is more critical. The wafer alignment is one of the important elements that impact overlay accuracy. In this paper, an evaluation of alignment performance was performed using various alignment marks placed in the scribe-line of short-loop wafers used for SilTerra 130 nm process. The alignment(More)
  • 1