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- S. J. Abou-Samra, A. Guyot
- 1998

Performance and complexity are considered here as two orthogonal axes. Performance metrics are recalled. Then different complexity metrics and scales are proposed. Different definitions of complexity are used depending on the considered level of abstraction. Finally, SOI and bulk CMOS technologies are compared in this space.

This chapter will first address the following issues: why a voltage transition causes power dissipation, what causes a transition, what are useful and redundant transitions, how information redundancy may reduce the number of transitions, how to make information redundant by adding dependant bits, how to statistically measure the average number of… (More)

This paper will first address the following issues: why a voltage transition causes power dissipation, what causes a transition, what are useful and redundant transitions, how information redundancy may reduce the number of transitions, how to statistically measure the average number of transitions (or activity). In a second part, the paper will show the… (More)

- S. J. Abou-Samra, A. Guyot, B. Laurent
- 2007

Adder architectures are presented here by an unified formalism, and analysed from the delay, complexity and power consumption points of view. An analytical model for the power consumption is derived, assuming that it is proportional to the transition density [DHNT95]. The model is subsequently validated by simulation using a signal transition probabilities… (More)

This paper addresses three topics: First, a new three-dimensional CMOS-SOI on SOI technology is presented, then design methodologies are proposed for this technology and last, a comparison is carried out between 2D and 3D designs. In this technology the P-channel devices are stacked over the N-channel ones. All gates are l00nm length. New design constraints… (More)

This paper will first address the issues: why a voltage transition causes power dissipation, what causes a transition, what are useful and redundant transitions, how information redundancy may reduce the number of transitions, how to make information redundant by adding dependant bits, how to statistically measure the average number of transitions (or… (More)

Adder architectures are presented here by an unified formalism, and analysed from the delay, complexity and power consumption points of view. An analytical model for the power consumption is derived, assuming that it is proportional to the transition density [DHNT95]. Finally, spurious transitions are taken into account when transitions at the input of a… (More)

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